Prof. Dr. Andreas Herkersdorf
Academic Career and Research Areas
The Chair of Prof. Herkersdorf (b. 1961) conducts research into architectures, coprocessors, design methods and design evaluation tools for application-specific multicore processors. IP packet switch nodes, embedded automotive electronics systems and visual computing are the main target applications. In addition, his Chair has proven expertise in prototype development on FPGA platforms, bio-inspired, self-organizing MPSoC solutions and techniques to improve fault tolerance and energy efficiency at system level.
After studying electrical engineering at TUM, he did his doctorate in 1991 at the Swiss Federal Institute of Technology Zurich. He then joined the research team at IBM Research – Zurich in the communication systems department. After that, he became manager of the network processor hardware group in IBM’s research division. Since 2003, Prof. Herkersdorf has held the Chair of Integrated Systems at TUM and is a member of the teaching staff of the Department of Computer Science. He sits on the editorial board of various international trade journals. He is the European representative of the IEEE/ACM ICCAD executive committee and a member of the CAR@TUM joint program of TUM and the BMW Group. Since April 2012 he has been a member of the Review Board “Computer Architecture and Embedded Systems“ of the German Research Foundation (DFG).
- IBM Outstanding Technical Achievement Award (2001)
- IBM Master Inventor (1998)
- IBM Innovation Achievement Award (viermal, 1996-2003)
Wang Z, Herkersdorf A: “An efficient approach for system-level timing simulation of compiler-optimized embedded software”. 46th Design Automation Conference (DAC 09), San Francisco, USA, July 26-31, 2009.
Wild T, Herkersdorf A, Lee GY: “TAPES – Trace-based architecture performance evaluation with SystemC”. Design Automation for Embedded Systems, Special Issue on SystemC-based System Modeling, Verification and Synthesis. 2006; 10(2–3): 157–179.Abstract
Taylor DE, Herkersdorf A, Döring A, Dittmann G: “Robust header compression (ROHC) in next-generation network processors”. IEEE/ACM Transactions on Networking. 2005; 13(4): 755–768.Abstract
Ohlendorf R, Herkersdorf A, Wild T: “FlexPath NP – a network processor concept with application-driven flexible processing paths”. CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005.Abstract
Chakraborty S, Künzli S, Thiele L, Herkersdorf A, Sagmeister P: “Fast and accurate performance evaluation of network processor architectures: combining simulations with analytical estimation”. Computer Networks. 2003; 41(5): 641–665.Abstract